The register bank

The register bank

At the heart of the Wireworld computer design is a register bank. It consists of 64 registers each of which can contain a 16-bit number. As we’ll see later, some of the registers have special functions; but first, we’ll look at how the general-purpose registers work.

section of register bank

The picture shows just the top seven registers in the bank. The data are stored on loops which are exactly the right size to hold 16 bits, which circulate continuously. The bank is shown idle. We will now describe in outline how the register bank is read from and written to: you can study the circuit if you wish to understand the processes in more detail.

Read cycles

Read cycles are handled by the logic on the left of the register bank. A read is initiated by sending a series of 16 pulses up the outermost wire on the left-hand side, and, after a short delay, a further series of 16 pulses up the inner wire. When the pulses on the outer wire reach the top of the bank, they are turned around and sent back down the inner wire. At some point the two trains of pulses will collide and annihilate one another: where this happens depends on the delay between their being sent out.

The first layer of logic in from the left edge detects when the two pulse trains are about to collide and generates a trigger signal. This signal is only generated at one point in the register bank, and is used to select the register to be read. The controller (not shown in this picture, but which sits below the register bank) can therefore trigger any desired register by allowing a suitable delay between sending out the pulse trains.

The data in the selected register flow down the chain of AND-NOT gates on the left until they reach the bottom, where they are received by the controller.

Observe that the time between the first read pulse being emitted and the read data arriving back at the controller is constant: it does not depend on which register is read.

Write cycles

The logic for write cycles, which is on the right-hand side of the register bank, is similar. The wanted register is selected with two wires using the same delayed-pulse strategy. An additional wire (the one on the far right) runs to the top of the register bank carrying the data to be written. These data flow down through the chain of AND-NOT gates in the write logic until they arrive at the selected register. The data are then written into the register loop using a combination of OR and AND-NOT gates to set and clear bits respectively.

Next: the instruction set.

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This page most recently updated Mon 16 Jan 11:10:09 GMT 2017
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